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Test questions
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1. What fragment corresponds to definition of the Gray code?
| A | B | C | D | E | |||||||||||||||
| x | y | F | x | y | F | x | Y | F | x | y | F | x | y | F | |||||
2. A code converter is a circuit that
A. makes the several systems compatible
B. makes the two systems compatible
C. makes the two systems compatible even though each uses a different binary code
D. makes the two systems compatible even though each uses a different codes
E. makes the several systems compatible even though each uses a different binary codes
3. Decimal 3 will be represented in 8, 4, -2, -1 code as
A. 0111 B. 0101 C. 0110 D. 0100 E. 1000
4. What factor is, as a rule, more important for the circuit?
A. number of gates B. Types of gates C. Propagation delay
D. number of levels of implementation D. None of above mentioned
5. In biquinary code decimal 2 is
A. 0100100 B. 0010010 C. 0100101 D. 1000010 E. 1000001
6. Binary conversion of decimal 12 is _______, the coding it in BCD is _____.
A. 1101, 00010011 B. 1101, 1100 C. 1101, 1111 D. 1100, 01101100
E. 1100, 00010010
7. In the table below you can see a message. Show the parity bit for rows 1 to 3 if odd parity system is adopted.
A. 0, 0, 1 B.1, 0, 1 C.1, 1, 0 D.0, 1, 0 E. 0, 1, 1
| Message | Parity bit |
8. Decimal 1 will be represented in Excess-3 code as
A. 0111 B. 0101 C. 0110 D. 0100 E. 1110
9. Binary combination of decimal 5 in Excess –3 code means decimal ______ for 8, 4, -2, -1 code.
A. 2 B. 3 C. 4 D. 6 E. 8
10. Decimal 9 will be represented in 2, 4, 2, 1 code as
A. 0111 B. 0101 C. 0110 D. 1100 E. 1111
LABORATORY WORK # 5.
FOUR-BIT BINARY PARALLEL ADDER.
Aims: investigate 4-bit binary parallel adder operation; make an addition according to the task. Compare the results of the addition with ones, made by theoretical way.
PREPARATION TO LAB WORK.
1 Learn the information about adders.
2 Draw look-ahead carry generator scheme with application of Scheme Design System.
3 Consider experiment’s scheme and analyze its operation. Draw it using Scheme Design System.
4 Draw the scheme of 8-bit binary parallel adder on the basis of 7483 chip with application of Scheme Design System. It will be the scheme for experiment 5B.
5 Answer the questions below in written form.
5.1 What is a half-(full-) adder?
5.2 Show the truth table for half-(full-) adder.
5.3 Show the algebraic expressions for sum and carry for half-(full-) adder.
5.4 What is a binary parallel adder?
5.5 What is a serial adder?
5.6 How many adders are needed to construct 7-bit parallel adder?
5.7 How many bits have typical full-adders ICs got?
5.8 How to connect IC’s full-adders if one package is not enough?
5.9 What is a look-ahead carry generator?
5.10 What functions can look-ahead carry generator produce?
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